SiPearl Selects Ansys’ Power Signoff Solution for European Supercomputer Chip
SiPearl will apply Ansys’ industry-leading multiphysics platform to meet power and reliability goals on Europe’s new state-of-the-art microprocessor
Key Highlights
- SiPearl is adopting Ansys Redhawk-SC semiconductor software to meet aggressive low-power goals for designing Europe’s new energy-efficient microprocessor for exascale supercomputing
- Ansys’ high predictive accuracy multiphysics simulation platform is used to minimize chip power and ensure operational reliability
- SiPearl will use Ansys’ solution to develop high-performance computing chips with advanced-node semiconductor technology
Ansys (NASDAQ: ANSS) has been selected by SiPearl to enable the development of its world-class high-performance computing (HPC) microprocessor family as part of the European Processor Initiative (EPI) consortium for exascale supercomputing. SiPearl will leverage the best-in-class Ansys RedHawk-SC™ multiphysics simulation platform to validate semiconductor power integrity, minimize power consumption, and accelerate development time of its Rhea family of microprocessors.
Rhea is a high-performance, low-power family of microprocessors that will assert Europe’s technological sovereignty in mission-critical semiconductors. SiPearl will use the Ansys RedHawk-SC power integrity and reliability platform for multiphysics signoff to develop Rhea. SiPearl’s system-on-chip (SoC) will power the European supercomputer to perform an astounding 1 quintillion calculations per second.
“Ansys’ industry-leading simulation platform will enable us to ensure the low-power performance and reliability of our microprocessor,” said Philippe Notton, CEO and founder of SiPearl. “With Ansys’ world-class RedHawk-SC signoff solution, we can achieve industry-leading performance and deliver our prototype in a timely manner to power Europe’s supercomputer of the future.”
SiPearl collaborates with its 27 EPI partners – scientific community, supercomputing centers and leading names from the IT, electronics, and automotive industries – to develop a first-generation family of microprocessors, known as Rhea, by 2022-2023, and plans to launch a second-generation family of microprocessors, known as Cronos, in 2023-2024.
“Power management has become an essential primary concern for chip designers at advanced silicon processes,” said John Lee, vice president and general manager of the electronics, semiconductor, and optics business unit at Ansys. “We are collaborating with the silicon foundries and major semiconductor customers to develop our high-capacity simulation platforms that integrate multiple physical effects to ensure high-fidelity results and the fastest time-to-results.”
This content was first published on the Ansys website.
